EE 647/647L HDL Design/Lab

Credits: (2.5-0.5) 3

This course explores modern design techniques utilizing hardware description languages (HDLs) such as VHDL, VHDL-A, and Verilog. Fundamentals language syntax will be covered in addition to advanced language constructs. Various hierarchical design styles such as dataflow, structural, and behavioral descriptions will be presented. Emphasis will be placed on both design simulation and synthesis. Synthesis platforms (e.g., FPGAs and ASICs) will also be examined. Other current issues will also be discussed such as reconfigurability, system-on-a-chip solutions, testbenches, soft processors, etc.

Prerequisites: CENG 342/342L or permission of instructor.
Corequisites: EE 647L

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